DIC_final_project/maze_solver_code_report.md

Maze Solver Code Report

An explanation of our SystemVerilog code for our 16x16 expandable maze solver chip.

Code Organization

Our maze solver code is organized hierarchically as follows:

    // FSM declaration
    module fsm_design;
    
    // Datapath component declarations
    module reg_nbit;
    module add_sub_wrap_nbit;
    module not_left_nbit;
    module bit_sel_4bit;
    module not_4bit;
    module nor_4bit;
    module move_conv_logic;
    module back_test_logic;
    module split_1_to_2_nbit;
    module stack_ncell;
    
    // Datapath declaration
    module datapath_design (
       	reg_nbit cur_wall_reg,
       	rot_left_4bit rotate_wall,
       	reg_nbit abs_dir_reg,
       	not_4bit wall_invert,
       	bit_sel_4bit test_move,
       	nor_4bit wall_check,
        reg_nbit rel_move_reg,
        reg_nbit abs_move_buf,
        reg_nbit rel_to_abs_alu,
        move_conv_logic move_conv,
        add_sub_wrap_nbit cur_to_next_alu,
        reg_nbit cur_addr_reg,
        reg_nbit next_addr_reg,
        split_1_to_2_nbit addr_split,
        back_test_logic back_test,
        stack_ncell stack,
        reg_nbit sol_reg
    );
    
    module chip_design (
        fsm_design controller,
        datapath_design datapath
    );

Our highest-level module, chip_design, is at the bottom of the .sv file to preserve Verilog hierarchical organization rules, where the components of a module are declared above the module.