50 lines
1.4 KiB
Markdown
50 lines
1.4 KiB
Markdown
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# Maze Solver Code Report
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*An explanation of our SystemVerilog code for our 16x16 expandable maze solver chip.*
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## Code Organization
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Our maze solver code is organized hierarchically as follows:
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```SystemVerilog
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// FSM declaration
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module fsm_design;
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// Datapath component declarations
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module reg_nbit;
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module add_sub_wrap_nbit;
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module not_left_nbit;
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module bit_sel_4bit;
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module not_4bit;
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module nor_4bit;
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module move_conv_logic;
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module back_test_logic;
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module split_1_to_2_nbit;
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module stack_ncell;
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// Datapath declaration
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module datapath_design (
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reg_nbit cur_wall_reg,
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rot_left_4bit rotate_wall,
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reg_nbit abs_dir_reg,
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not_4bit wall_invert,
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bit_sel_4bit test_move,
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nor_4bit wall_check,
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reg_nbit rel_move_reg,
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reg_nbit abs_move_buf,
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reg_nbit rel_to_abs_alu,
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move_conv_logic move_conv,
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add_sub_wrap_nbit cur_to_next_alu,
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reg_nbit cur_addr_reg,
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reg_nbit next_addr_reg,
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split_1_to_2_nbit addr_split,
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back_test_logic back_test,
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stack_ncell stack,
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reg_nbit sol_reg
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);
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module chip_design (
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fsm_design controller,
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datapath_design datapath
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);
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```
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Our highest-level module, chip_design, is at the bottom of the .sv file to preserve Verilog hierarchical organization rules, where the components of a module are declared above the module.
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