owendor/DIC_final_project
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A variable-size maze solver made in SystemVerilog, fabricated by TSMC in Spring 2026.
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  • SystemVerilog 100%
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Filename Latest commit message Latest commit date
Owen Dorweiler 56ff930a4a Added completed files
2025-12-07 17:52:28 -05:00
chip_design_tb_working.sv Added completed files 2025-12-07 17:52:28 -05:00
chip_design_working_variable.sv Added completed files 2025-12-07 17:52:28 -05:00
README.md Initial commit 2025-12-07 21:40:47 +00:00

README.md

dic_final_project

A variable-size maze solver made in SystemVerilog, manufactured by TSMC in Spring 2026.