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160
chip_design_tb_working.sv
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160
chip_design_tb_working.sv
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// Code your testbench here
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// or browse Examples
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module chip_design_tb #(
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parameter int N_x = 8,
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parameter int N_y = 8,
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parameter int N = N_x*N_y,
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parameter int N_width = N_x_width*N_y_width,
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parameter int DELAY_NS = 50
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);
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logic clk, rst, start, input_enable;
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logic [3:0] cur_wall;
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logic done, req_next_addr, out_val;
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logic [3:0] next_x, next_y;
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logic [1:0] solution;
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logic [3:0] maze[0:N_x-1][0:N_y-1];
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chip_design chip_design_uut (
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.clk(clk),
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.rst(rst),
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.start(start),
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.input_enable(input_enable),
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.cur_wall(cur_wall),
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.done(done),
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.req_next_addr(req_next_addr),
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.out_val(out_val),
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.next_x(next_x),
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.next_y(next_y),
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.solution(solution)
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);
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initial begin
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//"HARD" MAZE
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maze[0][0] = 4'b0011;
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maze[1][0] = 4'b1010;
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maze[2][0] = 4'b1010;
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maze[3][0] = 4'b1010;
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maze[4][0] = 4'b0010;
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maze[5][0] = 4'b1010;
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maze[6][0] = 4'b1010;
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maze[7][0] = 4'b0110;
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maze[0][1] = 4'b0101;
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maze[1][1] = 4'b1011;
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maze[2][1] = 4'b0110;
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maze[3][1] = 4'b0011;
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maze[4][1] = 4'b1100;
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maze[5][1] = 4'b0111;
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maze[6][1] = 4'b0111;
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maze[7][1] = 4'b0101;
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maze[0][2] = 4'b0101;
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maze[1][2] = 4'b0111;
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maze[2][2] = 4'b1001;
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maze[3][2] = 4'b1100;
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maze[4][2] = 4'b0011;
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maze[5][2] = 4'b1100;
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maze[6][2] = 4'b0101;
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maze[7][2] = 4'b0101;
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maze[0][3] = 4'b0101;
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maze[1][3] = 4'b0101;
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maze[2][3] = 4'b1011;
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maze[3][3] = 4'b0010;
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maze[4][3] = 4'b1000;
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maze[5][3] = 4'b0010;
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maze[6][3] = 4'b1100;
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maze[7][3] = 4'b0101;
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maze[0][4] = 4'b0101;
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maze[1][4] = 4'b1001;
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maze[2][4] = 4'b0110;
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maze[3][4] = 4'b1001;
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maze[4][4] = 4'b1110;
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maze[5][4] = 4'b1001;
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maze[6][4] = 4'b1010;
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maze[7][4] = 4'b0100;
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maze[0][5] = 4'b0101;
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maze[1][5] = 4'b0011;
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maze[2][5] = 4'b1000;
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maze[3][5] = 4'b0010;
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maze[4][5] = 4'b1010;
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maze[5][5] = 4'b0110;
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maze[6][5] = 4'b0111;
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maze[7][5] = 4'b0101;
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maze[0][6] = 4'b0101;
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maze[1][6] = 4'b1001;
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maze[2][6] = 4'b0110;
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maze[3][6] = 4'b1001;
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maze[4][6] = 4'b0110;
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maze[5][6] = 4'b1001;
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maze[6][6] = 4'b1100;
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maze[7][6] = 4'b0101;
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maze[0][7] = 4'b1001;
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maze[1][7] = 4'b0000;
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maze[2][7] = 4'b1001;
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maze[3][7] = 4'b1110;
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maze[4][7] = 4'b1001;
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maze[5][7] = 4'b1010;
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maze[6][7] = 4'b1010; // GOAL CELL
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maze[7][7] = 4'b1100;
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end
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always #(DELAY_NS) clk = ~clk;
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always @(posedge clk) begin
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if(req_next_addr) begin
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cur_wall <= maze[next_x][next_y];
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input_enable <= 1;
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end else begin
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input_enable <= 0;
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end
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end
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initial begin
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$dumpfile("dump.vcd");
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$dumpvars;
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rst = 1;
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clk = 0;
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start = 0;
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input_enable = 0;
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repeat (5) @(posedge clk);
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rst = 0;
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start = 1;
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@(posedge clk);
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start = 0;
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wait(done == 1);
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$display("Maze solve complete!");
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$finish;
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end
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int output_count = 1;
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initial begin
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forever begin
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@(posedge out_val);
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$display($sformatf("Move %0d: %b", output_count, solution));
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output_count++;
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end
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end
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endmodule
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662
chip_design_working_variable.sv
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662
chip_design_working_variable.sv
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@ -0,0 +1,662 @@
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// Max maze size parameter; must be power of 2
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`define MAX_SIZE 16
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// Start of FSM
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// Step 0a - Create a module with input / output variable
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module fsm_design (
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// Step 1b - Define all inputs and outputs
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input logic [0:0] back_flag,
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input logic clk,
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input logic input_enable,
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input logic no_walls,
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input logic rst,
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input logic stack_ptrs_eq,
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input logic start,
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input logic val_move,
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output logic cur_wall_reg_en,
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output logic next_addr_reg_en,
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output logic rel_move_reg_en,
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output logic abs_move_buf_en,
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output logic req_next_addr,
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output logic sol_reg_en,
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output logic stack_en,
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output logic stack_op,
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output logic stack_sol_inc,
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output logic update_reg,
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output logic [1:0] move_sel,
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output logic done,
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output logic out_val
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);
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// step 2 - Create the State Machine Information
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// Step 2a - Create the enum for all the states
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// Note: It is industry convention to put IDLE first, but I put S0 ... S7 first
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// So that the output waveforms are easier to read for students (S0 being state 0, and so on)
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typedef enum logic [3:0] {
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IDLE, INPUT, LOAD, RIGHT, UP, LEFT, DOWN, CHECK, PUSH, POP, UPDATE, LAST, OUTPUT, DONE
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} state_t;
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// Step 2b - Create the state variables for the current and next states
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state_t state, next_state;
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always_ff @(posedge clk) begin
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if (rst) state <= IDLE;
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else state <= next_state;
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end
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always_comb begin
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next_state = state;
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req_next_addr = 1'b0;
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cur_wall_reg_en = 1'b0;
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rel_move_reg_en = 1'b0;
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next_addr_reg_en = 1'b0;
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update_reg = 1'b0;
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stack_en = 1'b0;
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stack_op = 1'b0;
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stack_sol_inc = 1'b0;
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sol_reg_en = 1'b0;
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move_sel = 2'b00;
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done = 1'b0;
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out_val = 1'b0;
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abs_move_buf_en = 1'b0;
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case(state)
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IDLE:
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begin
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if (start) begin
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next_state = INPUT;
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end else begin
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next_state = IDLE;
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end
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end
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INPUT:
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begin
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req_next_addr = 1'b1;
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if (input_enable) begin
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next_state = LOAD;
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end else begin
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next_state = INPUT;
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end
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end
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LOAD:
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begin
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cur_wall_reg_en = 1'b1;
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if (no_walls) begin
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next_state = LAST;
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end
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else begin
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next_state = RIGHT;
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end
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end
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RIGHT:
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begin
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move_sel = 2'b01;
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rel_move_reg_en = val_move;
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if (val_move) begin
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next_state = CHECK;
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end
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else begin
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next_state = UP;
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end
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end
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UP:
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begin
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move_sel = 2'b00;
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rel_move_reg_en = val_move;
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if (val_move) begin
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next_state = CHECK;
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end
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else begin
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next_state = LEFT;
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end
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end
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LEFT:
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begin
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move_sel = 2'b11;
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rel_move_reg_en = val_move;
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if (val_move) begin
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next_state = CHECK;
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end
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else begin
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next_state = DOWN;
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end
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end
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DOWN:
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begin
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move_sel = 2'b10;
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rel_move_reg_en = val_move;
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begin
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next_state = CHECK;
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end
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end
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CHECK:
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begin
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abs_move_buf_en = 1'b1;
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if (back_flag && !stack_ptrs_eq) begin
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next_state = POP;
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end
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else begin
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next_state = PUSH;
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end
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end
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PUSH:
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begin
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stack_en = 1'b1;
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stack_op = 1'b0;
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next_addr_reg_en = 1'b1;
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begin
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next_state = UPDATE;
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end
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end
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POP:
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begin
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stack_en = 1'b1;
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stack_op = 1'b1;
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next_addr_reg_en = 1'b1;
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begin
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next_state = UPDATE;
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end
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end
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UPDATE:
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begin
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update_reg = 1'b1;
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begin
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next_state = INPUT;
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end
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end
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LAST:
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begin
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sol_reg_en = 1'b1;
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if (stack_ptrs_eq) begin
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next_state = DONE;
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end
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else begin
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next_state = OUTPUT;
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end
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end
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OUTPUT:
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begin
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stack_sol_inc = 1'b1;
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out_val = 1'b1;
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begin
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next_state = LAST;
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end
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end
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DONE:
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begin
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done = 1'b1;
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next_state = DONE;
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end
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endcase
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end
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endmodule
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// Start of datapath
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module reg_nbit #(
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parameter N = 8 // default to 8 bits
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) (
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input wire reg_clk,
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input wire reg_en,
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input wire reg_rst,
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input wire [N-1:0] reg_in,
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output logic [N-1:0] reg_out
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);
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always_comb begin
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if (reg_rst) begin
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reg_out <= {N{1'b0}}; // zero register on rst signal
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end
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else if (reg_en) begin
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reg_out <= reg_in; // update reg on en signal
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end
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end
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endmodule
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module add_sub_wrap_nbit #(
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parameter N = 2
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) (
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input wire [N-1:0] a_in,
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input wire [N-1:0] b_in,
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input wire add_sub_sel,
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output logic [N-1:0] result
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);
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assign result = add_sub_sel ? (a_in - b_in) : (a_in + b_in);
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endmodule
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module rot_left_4bit (
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input wire [3:0] rot_in,
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input wire [1:0] rot_val, // value to rotate by
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output logic [3:0] rot_out
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);
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assign rot_out = (rot_in << rot_val) | (rot_in >> (4 - rot_val));
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endmodule
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module bit_sel_4bit (
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input wire [3:0] sel_in,
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input wire [1:0] sel_val, // bit to select
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output logic sel_out
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);
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always_comb begin
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case (sel_val)
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2'b00: sel_out = sel_in[3]; // "up" direction
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2'b01: sel_out = sel_in[2]; // "right" direction
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2'b10: sel_out = sel_in[1]; // "left" direction
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2'b11: sel_out = sel_in[0]; // "down" direction
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default: sel_out = 1'b0; // default case
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endcase
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end
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endmodule
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module not_4bit (
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input wire [3:0] not_in,
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output logic [3:0] not_out
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);
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assign not_out = ~not_in;
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endmodule
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module nor_4bit (
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input wire [3:0] nor_in,
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output logic nor_out
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);
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assign nor_out = ~(|nor_in);
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endmodule
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module move_conv_logic #(
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parameter COOR_WIDTH = 4
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) (
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input wire [1:0] move_in,
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output logic [(COOR_WIDTH*2)-1:0] x_y,
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output logic add_sub // 0 for add, 1 for sub
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);
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logic [COOR_WIDTH-1:0] add_x;
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logic [COOR_WIDTH-1:0] add_y;
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always_comb begin
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case (move_in)
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2'b00: begin // up
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add_sub = 0;
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add_x = 0;
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add_y = 1;
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end
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2'b01: begin // right
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add_sub = 0;
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add_x = 1;
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add_y = 0;
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end
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2'b10: begin // down
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add_sub = 1;
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add_x = 0;
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add_y = 1;
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end
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2'b11: begin // left
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add_sub = 1;
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add_x = 1;
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add_y = 0;
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end
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default: begin // default case
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add_sub = 0;
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add_x = 0;
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add_y = 0;
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end
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endcase
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end
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assign x_y = {add_x, add_y}; // recombine x and y into one output
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endmodule
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module back_test_logic (
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input wire [1:0] cur_in,
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input wire [1:0] prev_in,
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output logic backtrack
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);
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// If cur_in and prev_in are different but have the same LSB, chip is backtracking
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assign backtrack = (cur_in != prev_in) && (cur_in[0] == prev_in[0]);
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endmodule
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module split_1_to_2_nbit #(
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parameter N = 8
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) (
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input wire [N-1:0] split_in,
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output wire [(N-1)/2:0] split_high_out,
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output wire [(N-1)/2:0] split_low_out
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);
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assign split_high_out = split_in[N-1:N/2];
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assign split_low_out = split_in[(N/2)-1:0];
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endmodule
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module stack_ncell #(
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parameter CELLS = 256
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) (
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input wire clk,
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input wire rst_stack,
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input wire stack_en, // High to enable push/pop operations
|
||||
input wire stack_op, // 0 for push, 1 for pop
|
||||
input wire [1:0] stack_in,
|
||||
input wire stack_sol_inc,
|
||||
output logic [1:0] stack_out,
|
||||
output logic [1:0] stack_sol,
|
||||
output logic stack_ptrs_eq
|
||||
);
|
||||
|
||||
localparam PTR_WIDTH = $clog2(CELLS);
|
||||
|
||||
logic [1:0] mem [0:CELLS-1];
|
||||
logic [PTR_WIDTH-1:0] stack_ptr;
|
||||
logic [PTR_WIDTH-1:0] stack_sol_ptr;
|
||||
|
||||
always_ff @(posedge clk or posedge rst_stack) begin
|
||||
if (rst_stack) begin
|
||||
stack_ptr <= 0;
|
||||
stack_sol_ptr <= 0;
|
||||
end else if (stack_sol_inc) begin
|
||||
stack_sol_ptr <= stack_sol_ptr + 1;
|
||||
end else if (stack_en) begin
|
||||
if (!stack_op) begin // Push Operation (stack_op is 0)
|
||||
// 1. Increment the stack pointer
|
||||
stack_ptr <= stack_ptr + 1;
|
||||
// 2. Write the input data to the new top location
|
||||
mem[stack_ptr + 1] <= stack_in;
|
||||
end else begin // Pop Operation (stack_op is 1)
|
||||
stack_ptr <= stack_ptr - 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign stack_out = mem[stack_ptr];
|
||||
assign stack_sol = mem[stack_sol_ptr + 1];
|
||||
assign stack_ptrs_eq = (stack_ptr == stack_sol_ptr);
|
||||
|
||||
endmodule
|
||||
|
||||
module datapath_logic (
|
||||
input wire [3:0] cur_wall,
|
||||
input wire cur_wall_reg_en,
|
||||
input wire [1:0] move_sel,
|
||||
input wire rel_move_reg_en,
|
||||
input wire abs_move_buf_en,
|
||||
input wire rst,
|
||||
input wire update_reg,
|
||||
input wire stack_en,
|
||||
input wire stack_op,
|
||||
input wire stack_sol_inc,
|
||||
input wire sol_reg_en,
|
||||
input wire next_addr_reg_en,
|
||||
input wire clk,
|
||||
|
||||
output logic [$clog2(`MAX_SIZE)-1:0] next_x,
|
||||
output logic [$clog2(`MAX_SIZE)-1:0] next_y,
|
||||
output logic [1:0] solution,
|
||||
output logic val_move,
|
||||
output logic stack_ptrs_eq,
|
||||
output logic no_walls,
|
||||
output logic [0:0] back_flag
|
||||
);
|
||||
|
||||
// Internal Wires
|
||||
logic [3:0] absolute_walls_wire;
|
||||
logic [1:0] absolute_dir_wire;
|
||||
logic [3:0] relative_walls_wire;
|
||||
logic [3:0] relative_walls_inv_wire;
|
||||
logic [1:0] absolute_move_wire;
|
||||
logic [1:0] absolute_move_buf_wire;
|
||||
logic [1:0] relative_move_wire;
|
||||
logic [($clog2(`MAX_SIZE)*2)-1:0] x_y_wire;
|
||||
logic add_sub_wire;
|
||||
logic [($clog2(`MAX_SIZE)*2)-1:0] current_address_wire;
|
||||
logic [($clog2(`MAX_SIZE)*2)-1:0] next_address_wire;
|
||||
logic [($clog2(`MAX_SIZE)*2)-1:0] next_full_wire;
|
||||
logic [1:0] prev_move_wire;
|
||||
logic [1:0] solution_wire;
|
||||
|
||||
reg_nbit #(.N(4)) cur_wall_reg (
|
||||
.reg_clk (clk),
|
||||
.reg_en (cur_wall_reg_en),
|
||||
.reg_rst (rst),
|
||||
.reg_in (cur_wall),
|
||||
.reg_out (absolute_walls_wire)
|
||||
);
|
||||
|
||||
rot_left_4bit rotate_wall (
|
||||
.rot_in (absolute_walls_wire),
|
||||
.rot_val (absolute_dir_wire),
|
||||
.rot_out (relative_walls_wire)
|
||||
);
|
||||
|
||||
reg_nbit #(.N(2)) abs_dir_reg (
|
||||
.reg_clk (clk),
|
||||
.reg_en (update_reg),
|
||||
.reg_rst (rst),
|
||||
.reg_in (absolute_move_buf_wire),
|
||||
.reg_out (absolute_dir_wire)
|
||||
);
|
||||
|
||||
not_4bit wall_invert (
|
||||
.not_in (relative_walls_wire),
|
||||
.not_out (relative_walls_inv_wire)
|
||||
);
|
||||
|
||||
bit_sel_4bit test_move (
|
||||
.sel_in (relative_walls_inv_wire),
|
||||
.sel_val (move_sel),
|
||||
.sel_out (val_move)
|
||||
);
|
||||
|
||||
nor_4bit wall_check (
|
||||
.nor_in (absolute_walls_wire),
|
||||
.nor_out (no_walls)
|
||||
);
|
||||
|
||||
reg_nbit #(.N(2)) rel_move_reg (
|
||||
.reg_clk (clk),
|
||||
.reg_en (rel_move_reg_en),
|
||||
.reg_rst (rst),
|
||||
.reg_in (move_sel),
|
||||
.reg_out (relative_move_wire)
|
||||
);
|
||||
|
||||
reg_nbit #(.N(2)) abs_move_buf (
|
||||
.reg_clk (clk),
|
||||
.reg_en (abs_move_buf_en),
|
||||
.reg_rst (rst),
|
||||
.reg_in (absolute_move_wire),
|
||||
.reg_out (absolute_move_buf_wire)
|
||||
);
|
||||
|
||||
add_sub_wrap_nbit #(.N(2)) rel_to_abs_alu (
|
||||
.a_in (relative_move_wire),
|
||||
.b_in (absolute_dir_wire),
|
||||
.add_sub_sel (1'b0),
|
||||
.result (absolute_move_wire)
|
||||
);
|
||||
|
||||
move_conv_logic #(.COOR_WIDTH($clog2(`MAX_SIZE))) move_conv (
|
||||
.move_in (absolute_move_buf_wire),
|
||||
.x_y (x_y_wire),
|
||||
.add_sub (add_sub_wire)
|
||||
);
|
||||
|
||||
add_sub_wrap_nbit #(.N($clog2(`MAX_SIZE)*2)) cur_to_next_alu (
|
||||
.a_in (current_address_wire),
|
||||
.b_in (x_y_wire),
|
||||
.add_sub_sel (add_sub_wire),
|
||||
.result (next_address_wire)
|
||||
);
|
||||
|
||||
reg_nbit #(.N($clog2(`MAX_SIZE)*2)) cur_addr_reg (
|
||||
.reg_clk (clk),
|
||||
.reg_en (update_reg),
|
||||
.reg_rst (rst),
|
||||
.reg_in (next_full_wire),
|
||||
.reg_out (current_address_wire)
|
||||
);
|
||||
|
||||
reg_nbit #(.N($clog2(`MAX_SIZE)*2)) next_addr_reg (
|
||||
.reg_clk (clk),
|
||||
.reg_en (next_addr_reg_en),
|
||||
.reg_rst (rst),
|
||||
.reg_in (next_address_wire),
|
||||
.reg_out (next_full_wire)
|
||||
);
|
||||
|
||||
split_1_to_2_nbit #(.N($clog2(`MAX_SIZE)*2)) addr_split (
|
||||
.split_in (next_full_wire),
|
||||
.split_high_out (next_x),
|
||||
.split_low_out (next_y)
|
||||
);
|
||||
|
||||
back_test_logic back_test (
|
||||
.cur_in (absolute_move_buf_wire),
|
||||
.prev_in (prev_move_wire),
|
||||
.backtrack (back_flag)
|
||||
);
|
||||
|
||||
stack_ncell #(.CELLS(`MAX_SIZE*`MAX_SIZE)) stack (
|
||||
.clk (clk),
|
||||
.rst_stack (rst),
|
||||
.stack_op (stack_op),
|
||||
.stack_en (stack_en),
|
||||
.stack_in (absolute_move_buf_wire),
|
||||
.stack_sol_inc (stack_sol_inc),
|
||||
.stack_out (prev_move_wire),
|
||||
.stack_sol (solution_wire),
|
||||
.stack_ptrs_eq (stack_ptrs_eq)
|
||||
);
|
||||
|
||||
reg_nbit #(.N(2)) sol_reg (
|
||||
.reg_clk (clk),
|
||||
.reg_en (sol_reg_en),
|
||||
.reg_rst (rst),
|
||||
.reg_in (solution_wire),
|
||||
.reg_out (solution)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
// Start of overall chip
|
||||
module chip_design (
|
||||
input logic clk,
|
||||
input logic [3:0] cur_wall,
|
||||
input logic input_enable,
|
||||
input logic rst,
|
||||
input logic start,
|
||||
|
||||
output logic req_next_addr,
|
||||
output logic [$clog2(`MAX_SIZE)-1:0] next_x,
|
||||
output logic [$clog2(`MAX_SIZE)-1:0] next_y,
|
||||
output logic [1:0] solution,
|
||||
output logic out_val,
|
||||
output logic done
|
||||
);
|
||||
|
||||
// Internal wires
|
||||
logic rel_move_reg_en_wire;
|
||||
logic abs_move_buf_en_wire;
|
||||
logic cur_wall_reg_en_wire;
|
||||
logic next_addr_reg_en_wire;
|
||||
logic [1:0] move_sel_wire;
|
||||
logic update_reg_wire;
|
||||
logic val_move_wire;
|
||||
logic stack_ptrs_eq_wire;
|
||||
logic no_walls_wire;
|
||||
logic [0:0] back_flag_wire;
|
||||
logic stack_en_wire;
|
||||
logic stack_op_wire;
|
||||
logic stack_sol_inc_wire;
|
||||
logic sol_reg_en_wire;
|
||||
|
||||
// Controller instance
|
||||
fsm_design controller (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.start (start),
|
||||
.input_enable (input_enable),
|
||||
.no_walls (no_walls_wire),
|
||||
.val_move (val_move_wire),
|
||||
.back_flag (back_flag_wire),
|
||||
.stack_ptrs_eq (stack_ptrs_eq_wire),
|
||||
|
||||
.req_next_addr (req_next_addr),
|
||||
.cur_wall_reg_en (cur_wall_reg_en_wire),
|
||||
.rel_move_reg_en (rel_move_reg_en_wire),
|
||||
.abs_move_buf_en (abs_move_buf_en_wire),
|
||||
.next_addr_reg_en (next_addr_reg_en_wire),
|
||||
.update_reg (update_reg_wire),
|
||||
.stack_en (stack_en_wire),
|
||||
.stack_op (stack_op_wire),
|
||||
.stack_sol_inc (stack_sol_inc_wire),
|
||||
.sol_reg_en (sol_reg_en_wire),
|
||||
.move_sel (move_sel_wire),
|
||||
.done (done),
|
||||
.out_val (out_val)
|
||||
);
|
||||
|
||||
// Datapath instance
|
||||
datapath_logic datapath (
|
||||
.cur_wall (cur_wall),
|
||||
.move_sel (move_sel_wire),
|
||||
.cur_wall_reg_en (cur_wall_reg_en_wire),
|
||||
.rel_move_reg_en (rel_move_reg_en_wire),
|
||||
.abs_move_buf_en (abs_move_buf_en_wire),
|
||||
.rst (rst),
|
||||
.update_reg (update_reg_wire),
|
||||
.stack_en (stack_en_wire),
|
||||
.stack_op (stack_op_wire),
|
||||
.stack_sol_inc (stack_sol_inc_wire),
|
||||
.sol_reg_en (sol_reg_en_wire),
|
||||
.next_addr_reg_en (next_addr_reg_en_wire),
|
||||
.clk (clk),
|
||||
|
||||
.next_x (next_x),
|
||||
.next_y (next_y),
|
||||
.solution (solution),
|
||||
.val_move (val_move_wire),
|
||||
.stack_ptrs_eq (stack_ptrs_eq_wire),
|
||||
.no_walls (no_walls_wire),
|
||||
.back_flag (back_flag_wire)
|
||||
);
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in a new issue