owendor/DIC_final_project
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A variable-size maze solver made in SystemVerilog, fabricated by TSMC in Spring 2026.
7 commits 1 branch 0 tags 3.4 MiB
  • SystemVerilog 100%
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Filename Latest commit message Latest commit date
Owen Dorweiler 108ab1b347 Added circuit and fsm diagrams
2025-12-08 16:13:04 -05:00
images Added circuit and fsm diagrams 2025-12-08 16:13:04 -05:00
chip_design_tb_working.sv Added comments 2025-12-07 18:00:45 -05:00
chip_design_working_variable.sv Update datapath_design declaration name 2025-12-07 20:05:48 -05:00
maze_solver_code_report.md First section of report.md 2025-12-07 20:30:17 -05:00
README.md Initial commit 2025-12-07 21:40:47 +00:00

README.md

dic_final_project

A variable-size maze solver made in SystemVerilog, manufactured by TSMC in Spring 2026.