156 lines
3.5 KiB
Systemverilog
156 lines
3.5 KiB
Systemverilog
// Code your testbench here
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// or browse Examples
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module chip_design_tb #(
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parameter int N_x = 8, // full maze size
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parameter int N_y = 8, // full maze size
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parameter int DELAY_NS = 50
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);
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logic clk, rst, start, input_enable;
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logic [3:0] cur_wall;
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logic done, req_next_addr, out_val;
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logic [3:0] next_x, next_y;
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logic [1:0] solution;
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logic [3:0] maze[0:N_x-1][0:N_y-1];
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chip_design chip_design_uut (
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.clk(clk),
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.rst(rst),
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.start(start),
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.input_enable(input_enable),
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.cur_wall(cur_wall),
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.done(done),
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.req_next_addr(req_next_addr),
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.out_val(out_val),
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.next_x(next_x),
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.next_y(next_y),
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.solution(solution)
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);
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initial begin
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//"HARD" MAZE
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maze[0][0] = 4'b0011;
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maze[1][0] = 4'b1010;
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maze[2][0] = 4'b1010;
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maze[3][0] = 4'b1010;
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maze[4][0] = 4'b0010;
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maze[5][0] = 4'b1010;
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maze[6][0] = 4'b1010;
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maze[7][0] = 4'b0110;
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maze[0][1] = 4'b0101;
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maze[1][1] = 4'b1011;
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maze[2][1] = 4'b0110;
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maze[3][1] = 4'b0011;
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maze[4][1] = 4'b1100;
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maze[5][1] = 4'b0111;
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maze[6][1] = 4'b0111;
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maze[7][1] = 4'b0101;
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maze[0][2] = 4'b0101;
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maze[1][2] = 4'b0111;
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maze[2][2] = 4'b1001;
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maze[3][2] = 4'b1100;
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maze[4][2] = 4'b0011;
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maze[5][2] = 4'b1100;
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maze[6][2] = 4'b0101;
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maze[7][2] = 4'b0101;
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maze[0][3] = 4'b0101;
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maze[1][3] = 4'b0101;
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maze[2][3] = 4'b1011;
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maze[3][3] = 4'b0010;
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maze[4][3] = 4'b1000;
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maze[5][3] = 4'b0010;
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maze[6][3] = 4'b1100;
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maze[7][3] = 4'b0101;
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maze[0][4] = 4'b0101;
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maze[1][4] = 4'b1001;
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maze[2][4] = 4'b0110;
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maze[3][4] = 4'b1001;
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maze[4][4] = 4'b1110;
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maze[5][4] = 4'b1001;
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maze[6][4] = 4'b1010;
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maze[7][4] = 4'b0100;
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maze[0][5] = 4'b0101;
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maze[1][5] = 4'b0011;
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maze[2][5] = 4'b1000;
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maze[3][5] = 4'b0010;
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maze[4][5] = 4'b1010;
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maze[5][5] = 4'b0110;
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maze[6][5] = 4'b0111;
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maze[7][5] = 4'b0101;
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maze[0][6] = 4'b0101;
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maze[1][6] = 4'b1001;
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maze[2][6] = 4'b0110;
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maze[3][6] = 4'b1001;
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maze[4][6] = 4'b0110;
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maze[5][6] = 4'b1001;
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maze[6][6] = 4'b1100;
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maze[7][6] = 4'b0101;
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maze[0][7] = 4'b1001;
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maze[1][7] = 4'b0000;
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maze[2][7] = 4'b1001;
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maze[3][7] = 4'b1110;
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maze[4][7] = 4'b1001;
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maze[5][7] = 4'b1010;
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maze[6][7] = 4'b1010; // GOAL CELL
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maze[7][7] = 4'b1100;
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end
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always #(DELAY_NS) clk = ~clk;
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always @(posedge clk) begin
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if(req_next_addr) begin
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cur_wall <= maze[next_x][next_y];
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input_enable <= 1;
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end else begin
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input_enable <= 0;
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end
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end
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initial begin
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$dumpfile("dump.vcd");
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$dumpvars;
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rst = 1;
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clk = 0;
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start = 0;
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input_enable = 0;
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repeat (5) @(posedge clk);
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rst = 0;
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start = 1;
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@(posedge clk);
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start = 0;
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wait(done == 1);
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$display("Maze solve complete!");
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$finish;
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end
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int output_count = 1;
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initial begin
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forever begin
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@(posedge out_val);
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$display($sformatf("Move %0d: %b", output_count, solution));
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output_count++;
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end
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end
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endmodule
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