Added comments

2025-12-09 14:14:49 -05:00 · 2025-12-09 14:14:49 -05:00 · 8d6f728abc
commit 8d6f728abc
parent 8e47edbe88
1 changed files with 1 additions and 1 deletions
--- a/chip_design_working_variable.sv
+++ b/chip_design_working_variable.sv
@ -236,7 +236,7 @@ module add_sub_wrap_nbit #(
 ) (
    input wire [N-1:0] a_in,
    input wire [N-1:0] b_in,
-    input wire         add_sub_sel,
+    input wire         add_sub_sel, // 0 = add, 1 = sub

    output logic [N-1:0] result
 );