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Owen Dorweiler 2025-12-09 14:14:49 -05:00
commit 8d6f728abc
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chip_design_working_variable.sv
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@ -236,7 +236,7 @@ module add_sub_wrap_nbit #(
) ( ) (
input wire [N-1:0] a_in, input wire [N-1:0] a_in,
input wire [N-1:0] b_in, input wire [N-1:0] b_in,
input wire add_sub_sel, input wire add_sub_sel, // 0 = add, 1 = sub
output logic [N-1:0] result output logic [N-1:0] result
); );